PIC16F916
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC16F916
CONFIG (address:0x2007, mask:0x1FFF, default:0x1FFF)
FOSC -- Oscillator Selection bits (bitmask:0x0007)
FOSC = LP | 0x3FF8 | LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT/T1OSO and RA7/OSC1/CLKIN/T1OSI.
FOSC = XT | 0x3FF9 | XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT/T1OSO and RA7/OSC1/CLKIN/T1OSI.
FOSC = HS | 0x3FFA | HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT/T1OSO and RA7/OSC1/CLKIN/T1OSI.
FOSC = EC | 0x3FFB | EC: I/O function on RA6/OSC2/CLKOUT/T1OSO pin, CLKIN on RA7/OSC1/CLKIN/T1OSI.
FOSC = INTOSCIO | 0x3FFC | INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT/T1OSO pin, I/O function on RA7/OSC1/CLKIN/T1OSI.
FOSC = INTOSCCLK | 0x3FFD | INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT/T1OSO pin, I/O function on RA7/OSC1/CLKIN/T1OSI.
FOSC = EXTRCIO | 0x3FFE | RCIO oscillator: I/O function on RA6/OSC2/CLKOUT/T1OSO pin, RC on RA7/OSC1/CLKIN/T1OSI.
FOSC = EXTRCCLK | 0x3FFF | RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT/T1OSO pin, RC on RA7/OSC1/CLKIN/T1OSI.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF | 0x3FF7 | WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
WDTE = ON | 0x3FFF | WDT enabled.
PWRTE -- Power Up Timer Enable bit (bitmask:0x0010)
PWRTE = ON | 0x3FEF | PWRT enabled.
PWRTE = OFF | 0x3FFF | PWRT disabled.
MCLRE -- RE3/MCLR pin function select bit (bitmask:0x0020)
MCLRE = OFF | 0x3FDF | RE3/MCLR pin function is digital input, MCLR internally tied to VDD.
MCLRE = ON | 0x3FFF | RE3/MCLR pin function is MCLR.
CP -- Code Protection bit (bitmask:0x0040)
CP = ON | 0x3FBF | Program memory code protection is enabled.
CP = OFF | 0x3FFF | Program memory code protection is disabled.
CPD -- Data Code Protection bit (bitmask:0x0080)
CPD = ON | 0x3F7F | Data memory code protection is enabled.
CPD = OFF | 0x3FFF | Data memory code protection is disabled.
BOREN -- Brown-out Reset Selection bits (bitmask:0x0300)
BOREN = OFF | 0x3CFF | BOR disabled.
BOREN = SBODEN | 0x3DFF | BOR controlled by SBOREN bit of the PCON register.
BOREN = NSLEEP | 0x3EFF | BOR enabled during operation and disabled in Sleep.
BOREN = ON | 0x3FFF | BOR enabled.
IESO -- Internal External Switchover bit (bitmask:0x0400)
IESO = OFF | 0x3BFF | Internal/External Switchover mode is disabled.
IESO = ON | 0x3FFF | Internal/External Switchover mode is enabled.
FCMEN -- Fail-Safe Clock Monitor Enabled bit (bitmask:0x0800)
FCMEN = OFF | 0x37FF | Fail-Safe Clock Monitor is disabled.
FCMEN = ON | 0x3FFF | Fail-Safe Clock Monitor is enabled.
DEBUG -- In-Circuit Debugger Mode bit (bitmask:0x1000)
DEBUG = ON | 0x2FFF | In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger.
DEBUG = OFF | 0x3FFF | In-Circuit Debugger disabled, RB6/ISCPCLK and RB7/ICSPDAT are general purpose I/O pins.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.